Dowrick, T, McDaid, LJ and Hall, S 
ORCID: 0000-0001-8387-1036
(2018)
Fan-in analysis of a leaky integrator circuit using charge transfer synapses.
Neurocomputing, 314.
78 - 85.
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Dowrick et al Neurocomputing 2018.pdf - Author Accepted Manuscript Download (331kB) |
Abstract
It is shown that a simple leaky integrator (LI) circuit operating in a dynamic mode can allow spatial and temporal summation of weighted synaptic outputs. The circuit incorporates a current mirror configuration to sum charge packets released from charge transfer synapses and an n-channel MOSFET, operating in subthreshold, serves to implement a leakage capability, which sets the decay time for the postsynaptic response. The focus of the paper is to develop an analytical model for fan-in and validate the model against simulation and experimental results obtained from a prototype chip fabricated in the AMS 0.35 μm mixed signal CMOS technology. We show that the model predicts the theoretical limit on fan-in, relates the magnitude of the postsynaptic response to weighted synaptic inputs and captures the transient response of the LI when stimulated with spike inputs.
| Item Type: | Article |
|---|---|
| Depositing User: | Symplectic Admin |
| Date Deposited: | 05 Sep 2018 06:39 |
| Last Modified: | 19 Jan 2023 01:25 |
| DOI: | 10.1016/j.neucom.2018.06.065 |
| URI: | https://livrepository.liverpool.ac.uk/id/eprint/3025878 |
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