Online Fault Tolerance Technique for TSV-Based 3-D-IC

Zhao, Y, Khursheed, S and Al-Hashimi, BM (2015) Online Fault Tolerance Technique for TSV-Based 3-D-IC. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 23 (8). 1567 - 1571. ISSN 1063-8210

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Item Type:	Article
Uncontrolled Keywords:	3-D, delay test, fault tolerance, online test, through-silicon-vias (TSV)
Depositing User:	Symplectic Admin
Date Deposited:	07 Sep 2015 09:04
Last Modified:	31 Oct 2018 10:28
DOI:	10.1109/TVLSI.2014.2343156
URI:	http://livrepository.liverpool.ac.uk/id/eprint/2024262

Available Versions of this Item

• Online Fault Tolerance Technique for TSV-Based 3-D-IC. (deposited 07 Sep 2015 09:04) [Currently Displayed]
  • Online Fault Tolerance Technique for TSV-Based 3-D-IC. (deposited 28 Apr 2016 08:25)

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