Delay test for diagnosis of power switches

Khursheed, S ORCID: 0000-0002-5720-0607, Shi, K, Al-Hashimi, BM, Wilson, PR and Chakrabarty, K (2014) Delay test for diagnosis of power switches IEEE Transactions on Very Large Scale Integration VLSI Systems, 22 (2). pp. 197-206. ISSN 1063-8210, 1557-9999

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Abstract

Power switches are used as a part of the power-gating technique to reduce the leakage power of a design. To the best of our knowledge, this is the first report in open literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes the recently proposed design-for-test solution for efficient testing of power switches in the presence of process, voltage, and temperature variation. It divides power switches into segments such that any faulty power switch is detectable, thereby achieving high diagnosis accuracy. The proposed diagnosis method is validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that, when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; it is less than 12% when considering VT variations. © 1993-2012 IEEE.

Item Type:	Article
Uncontrolled Keywords:	Design for test (DFT), diagnosis, leakage power management, power gating, sleep transistor
Depositing User:	Symplectic Admin
Date Deposited:	07 Sep 2015 08:53
Last Modified:	01 Mar 2026 06:22
DOI:	10.1109/TVLSI.2013.2239319
Related Websites:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/2024264
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