Gate-Sizing-Based Single V-dd Test for Bridge Defects in Multivoltage Designs



Khursheed, Saqib, Al-Hashimi, Bashir M, Chakrabarty, Krishnendu and Harrod, Peter
(2010) Gate-Sizing-Based Single V-dd Test for Bridge Defects in Multivoltage Designs. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 29 (9). 1409 - 1421.

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Item Type: Article
Uncontrolled Keywords: Design for testability gate sizing, multiple-V-dd designs, resistive bridging faults, test cost
Depositing User: Symplectic Admin
Date Deposited: 07 Sep 2015 08:50
Last Modified: 16 Sep 2021 15:10
DOI: 10.1109/TCAD.2010.2059310
Related URLs:
URI: https://livrepository.liverpool.ac.uk/id/eprint/2024267