Gate-sizing-based single Vdd test for bridge defects in multivoltage designs

Khursheed, S ORCID: 0000-0002-5720-0607, Al-Hashimi, BM, Chakrabarty, K and Harrod, P (2010) Gate-sizing-based single Vdd test for bridge defects in multivoltage designs IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 29 (9). pp. 1409-1421. ISSN 0278-0070, 1937-4151

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Abstract

The use of multiple voltage settings for dynamic power management is an effective design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% fault coverage; however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective gate sizing technique for reducing test cost of multi-V<inf>dd</inf> designs with bridge defects. Using synthesized ISCAS and ITC benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves single V<inf>dd</inf> test, without affecting the fault coverage of the original test. In addition, the proposed technique performs better in terms of timing, area, and power than the recently proposed test point insertion technique. This is the first reported work that achieves single V<inf>dd</inf> test for resistive bridge defects, without compromising fault coverage in multi-V<inf>dd</inf> designs. © 2010 IEEE.

Item Type:	Article
Uncontrolled Keywords:	Design for testability gate sizing, multiple-V-dd designs, resistive bridging faults, test cost
Depositing User:	Symplectic Admin
Date Deposited:	07 Sep 2015 08:50
Last Modified:	01 Mar 2026 06:21
DOI:	10.1109/TCAD.2010.2059310
Related Websites:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/2024267
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