Efficient static compaction techniques for sequential circuits based on reverse-order restoration and test relaxation

El-Maleh, AH, Khursheed, SS ORCID: 0000-0002-5720-0607 and Sait, SM (2006) Efficient static compaction techniques for sequential circuits based on reverse-order restoration and test relaxation IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 25 (11). pp. 2556-2564. ISSN 0278-0070, 1937-4151

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Abstract

The authors present efficient reverse-order-restoration (ROR)-based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation-based restoration of test subsequences, the authors' technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using a state traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques. © 2006 IEEE.

Item Type:	Article
Uncontrolled Keywords:	fault coverage, linear reverse-order restoration (LROR), state traversal (ST), static compaction, test relaxation
Depositing User:	Symplectic Admin
Date Deposited:	07 Sep 2015 08:25
Last Modified:	01 Mar 2026 06:22
DOI:	10.1109/TCAD.2006.873895
Related Websites:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/2024271
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