DFT Architecture with Power-Distribution-Network Consideration for Delay-Based Power Gating Test

Tenentes, V, Khursheed, S ORCID: 0000-0002-5720-0607, Rossi, D, Yang, S and Al-Hashimi, BM (2015) DFT Architecture with Power-Distribution-Network Consideration for Delay-Based Power Gating Test IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 34 (12). pp. 2013-2024. ISSN 0278-0070, 1937-4151

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Abstract

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-Testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-To-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%-98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles.

Item Type:	Article
Uncontrolled Keywords:	Design-for-testability (DFT), grid style, power gating, power-distribution-network (PDN), ring style, systematic variations (SVs), test quality (TQ)
Depositing User:	Symplectic Admin
Date Deposited:	28 Apr 2016 08:22
Last Modified:	01 Mar 2026 00:47
DOI:	10.1109/TCAD.2015.2446939
Related Websites:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/3000954
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