Aging Benefits in Nanometer CMOS Designs

Rossi, D, Tenentes, V, Yang, S, Khursheed, S ORCID: 0000-0002-5720-0607 and Al-Hashimi, BM (2017) Aging Benefits in Nanometer CMOS Designs IEEE Transactions on Circuits and Systems II Express Briefs, 64 (3). pp. 324-328. ISSN 1549-7747, 1558-3791

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Abstract

In this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.

Item Type:	Article
Uncontrolled Keywords:	Bias temperature instability (BTI) aging, energy efficiency, leakage current, nanometer technology, static power
Depositing User:	Symplectic Admin
Date Deposited:	03 Jun 2016 09:00
Last Modified:	01 Mar 2026 05:36
DOI:	10.1109/TCSII.2016.2561206
Related Websites:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/3001494
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