Exercising Symbolic Discrete Control for Designing Low-power Hardware Circuits: an Application to Clock-gating

Özbaltan, Mete and Berthier, Nicolas ORCID: 0000-0002-0933-8193 (2018) Exercising Symbolic Discrete Control for Designing Low-power Hardware Circuits: an Application to Clock-gating. In: 14th Workshop on Discrete Event Systems, 2018-5-30 - 2018-6-1, Sorrento Coast, Italy.

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Abstract

We devise a tool-supported framework for achieving power-efficiency of hardware chips from high-level designs described using the popular hardware description language Verilog. We consider digital circuits as hierarchical compositions of sub-circuits, and achieve power-efficiency by switching-off the clock of each sub-circuit according to some clock-gating logic. We encode the computation of the latter as several small symbolic discrete controller synthesis problems, and use the resulting controllers to derive power-efficient versions from original circuit designs. We detail and illustrate our approach using a running example, and validate it experimentally by deriving a low-power version of an actual Reed-Solomon decoder.

Item Type:	Conference or Workshop Item (Unspecified)
Uncontrolled Keywords:	Symbolic Discrete Controller Synthesis, Digital Synchronous Circuits, Power-efficiency
Depositing User:	Symplectic Admin
Date Deposited:	11 Jun 2018 08:47
Last Modified:	19 Jan 2023 01:32
DOI:	10.1016/j.ifacol.2018.06.289
Related URLs:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/3022157