A Framework for TSV based 3D-IC to Analyze Aging and TSV Thermo-mechanical stress on Soft Errors

Reddy, Raviteja P, Acharyya, Amit and Khursheed, Saqib (2019) A Framework for TSV based 3D-IC to Analyze Aging and TSV Thermo-mechanical stress on Soft Errors. In: 2019 IEEE International Test Conference in Asia (ITC-Asia), 2019-9-3 - 2019-9-5, Tokyo, Japan.

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Official URL: http://dx.doi.org/10.1109/itc-asia.2019.00034

Abstract

The CMOS aging, transient effects, and TSV thermomechanical stress degrade the resilience of 3D-ICs. The transients effects lead to soft errors and aggravated with the CMOS Bias temperature instability (BTI). In this paper, we analyze detrimental transient and BTI effect on soft error rate (SER) in 3D-ICs. However, TSV thermomechanical stress presents a considerable benefit by enhancing the critical charge (Qc) and reduce the SER due to decrease in the threshold voltage and increase in mobility of carriers in transistor present out of keep-out-zone and useful range. Therefore we propose a framework to evaluate the effect of transient, BTI, and TSV thermomechanical stress on critical charge and SER in 3D-ICs. Subsequently, through HSPICE simulation we show that for a lifetime of ten years and on the topmost layer of stacked 3D-IC, the reduction in SER of NAND gate by 5.12% - 9.05% and in 6T SRAM 2.51% - 4.76% and 3.77% - 5.64% decrease for storing 0 and 1 respectively.

Item Type:	Conference or Workshop Item (Unspecified)
Uncontrolled Keywords:	3D-IC, Through-silicon via (TSV), Resilience, BTI, SER
Depositing User:	Symplectic Admin
Date Deposited:	04 Jul 2019 15:21
Last Modified:	17 Mar 2024 04:32
DOI:	10.1109/ITC-Asia.2019.00034
Related URLs:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/3048629