A Cost-Aware Framework for Lifetime Reliability of TSV-Based 3D-IC Design

Reddy, RP, Acharyya, A ORCID: 0000-0002-5636-0676 and Khursheed, S ORCID: 0000-0002-5720-0607 (2020) A Cost-Aware Framework for Lifetime Reliability of TSV-Based 3D-IC Design IEEE Transactions on Circuits and Systems II Express Briefs, 67 (11). pp. 2677-2681. ISSN 1549-7747, 1558-3791

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Abstract

The lifetime reliability of 3D-IC is limited due to defects, thermal issues and aging of Through-silicon-via (TSV). The state-of-The-Art methodologies for enhancing reliability are based on the fault tolerance techniques using redundant TSVs. The existing methodlogies do not consider the target lifetime, various failure mechanisms and workload. Thus the performance and cost of 3D-ICs is affected significantly. In this brief, we propose a TSV lifetime reliability aware 3D-IC framework with various TSV failure mechanisms and workload into consideration. Subsequently, validation and evaluation on IWLS'05 benchmark circuits is done for TSV lifetime reliability and compared with existing fault tolerance techniques to provide synergy between TSV count and targeted lifetime reliability of Router and Ring architectures.

Item Type:	Article
Uncontrolled Keywords:	Through-silicon vias, Failure analysis, Stress, Reliability engineering, Fault tolerant systems, Fault tolerance, 3D-IC, through-silicon-via (TSV), fault tolerance and lifetime reliability
Depositing User:	Symplectic Admin
Date Deposited:	10 Feb 2020 10:27
Last Modified:	01 Mar 2026 09:25
DOI:	10.1109/TCSII.2020.2970724
Related Websites:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/3073825
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