Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery



Yang, Sheng, Khursheed, Saqib, Al-Hashimi, Bashir M, Flynn, David and Idgunji, Sachin
(2011) Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 30 (12). pp. 1773-1785.

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Abstract

State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software, respectively. To validate the methodology, ARM Cortex-M0 embedded microprocessor (provided by our industrial project partner) is implemented in field-programmable gate array and further synthesized using 65-nm technology to quantify the cost in terms of area, latency, and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multibit errors for a wide range of fault rates. © 2006 IEEE.

Item Type: Article
Uncontrolled Keywords: Error correction, power gating, reliability, state retention, voltage scaling, voltage-scaled state retention
Depositing User: Symplectic Admin
Date Deposited: 07 Sep 2015 08:52
Last Modified: 16 Dec 2022 02:27
DOI: 10.1109/TCAD.2011.2166590
Related URLs:
URI: https://livrepository.liverpool.ac.uk/id/eprint/2024265