Zhao, Yi, Khursheed, Saqib and Al-Hashimi, Bashir M
(2015)
Online Fault Tolerance Technique for TSV-Based 3-D-IC.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 23 (8).
pp. 1567-1571.
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Abstract
This brief presents the design, validation, and evaluation of an efficient online fault tolerance technique for fault detection and recovery in presence of three through-silicon-vias (TSV) defects: 1) voids; 2) delamination between TSV and landing pad; and 3) TSV short-to-substrate. The technique employs transition delay test for TSV fault detection. Fault recovery is achieved by employing redundant TSVs and rerouting signals to fault-free TSVs. This technique is efficient because it requires a small ( 2 × number of TSVs per group) number of clock cycles for fault detection and recovery. Synthesis results using 130-nm design library show that 100% repair capability can be achieved with low area overhead (4% for the best case).
Item Type: | Article |
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Uncontrolled Keywords: | 3-D, delay test, fault tolerance, online test, through-silicon-vias (TSV) |
Depositing User: | Symplectic Admin |
Date Deposited: | 28 Apr 2016 08:25 |
Last Modified: | 16 Mar 2024 05:53 |
DOI: | 10.1109/TVLSI.2014.2343156 |
Related URLs: | |
URI: | https://livrepository.liverpool.ac.uk/id/eprint/3000952 |
Available Versions of this Item
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Online Fault Tolerance Technique for TSV-Based 3-D-IC. (deposited 07 Sep 2015 09:04)
- Online Fault Tolerance Technique for TSV-Based 3-D-IC. (deposited 28 Apr 2016 08:25) [Currently Displayed]