A compact spike-timing-dependent-plasticity circuit for floating gate weight implementation

Smith, AW, McDaid, LJ and Hall, S ORCID: 0000-0001-8387-1036 (2014) A compact spike-timing-dependent-plasticity circuit for floating gate weight implementation. NEUROCOMPUTING, 124. pp. 210-217.

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Abstract

Spike timing dependent plasticity (STDP) forms the basis of learning within neural networks. STDP allows for the modification of synaptic weights based upon the relative timing of pre- and post-synaptic spikes. A compact circuit is presented which can implement STDP, including the critical plasticity window, to determine synaptic modification. A physical model to predict the time window for plasticity to occur is formulated and the effects of process variations on the window is analyzed. The STDP circuit is implemented using two dedicated circuit blocks, one for potentiation and one for depression where each block consists of 4 transistors and a polysilicon capacitor. SpectreS simulations of the back-annotated layout of the circuit and experimental results indicate that STDP with biologically plausible critical timing windows over the range from 10. μs to 100. ms can be implemented. Also a floating gate weight storage capability, with drive circuits, is presented and a detailed analysis correlating weights changes with charging time is given. © 2013 Elsevier B.V.

Item Type:	Article
Additional Information:	## TULIP Type: Articles/Papers (Journal) ##
Uncontrolled Keywords:	Spike timing dependent plasticity, Neural networks, Floating gate, MOSFET
Depositing User:	Symplectic Admin
Date Deposited:	02 Feb 2017 11:53
Last Modified:	19 Jan 2023 07:19
DOI:	10.1016/j.neucom.2013.07.007
Related URLs:	Author Publisher
URI:	https://livrepository.liverpool.ac.uk/id/eprint/3005523