Intelligent Remaining Useful Lifetime Estimation and Built-in Self-Test for Reliable Digital Designs

Hernandez Martinez, Antonio (2022) Intelligent Remaining Useful Lifetime Estimation and Built-in Self-Test for Reliable Digital Designs. PhD thesis, University of Liverpool.

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Abstract

The integration of millions of transistors on a single chip is possible due to rapid scaling of CMOS technology. This is critical to the advancement of several disciplines, including medicine, automotive, aerospace, military and banking, which uses high performance and reliable microelectronics as part of design with up to 20 years of expected operational life. Reliability concerns have been addressed in research studies around the world, proposing testing and monitoring procedures for integrated circuits (ICs) as a way to avert catastrophic events. For example, built-in self-test (BIST) allows implementation of testing methods on-chip, making it feasible for on-site testing. This thesis contributes to this approach by proposing a technique for the test pattern generator. The Berleycamp-Messey (BM) algorithm is employed as a deterministic technique to find the generator of test patterns for hard to detect faults. Using test sets from an automatic test pattern generator (ATPG), a trade-off analysis is provided on re-seeding and concatenated test sets that demonstrate high test coverage at reduced area overhead, while maintaining full test coverage. The issue of remaining useful life (RUL) of electronic devices is a critical challenge for reliability. In practice, the mean time to failure (MTTF) is taken as a measure of electronics' anticipated longevity. Nonetheless, this technique involves broad assumptions that lead to RUL mispredictions. Similar deviations are found when using passive components to monitor lifetime of electronics. This thesis presents a machine learning based method that accurately predicts the RUL of each microelectronic device using minimal area overhead. This considers aging effects of CMOS transistors, as well as temperature and voltage variation. Embedded DRAM (eDRAM) is commonly employed in SoCs, accounting for over half of the total chip area. As a result, the critical effects of aging in eDRAM is also addressed in this thesis, showing a favourable influence on the data retention time (DRT) and therefore benefiting low power design methodology. A comprehensive analysis on DRT and refresh rate (RR) is provided, accounting for aging effects, process variation and temperature variation. A machine learning model is trained to predict RR and contributes to management and optimization over the lifetime of embedded DRAM.

Item Type:	Thesis (PhD)
Divisions:	Faculty of Science and Engineering > School of Electrical Engineering, Electronics and Computer Science
Depositing User:	Symplectic Admin
Date Deposited:	15 Dec 2022 15:31
Last Modified:	01 Jan 2024 02:31
DOI:	10.17638/03163695
Supervisors:	Khursheed, Saqib
URI:	https://livrepository.liverpool.ac.uk/id/eprint/3163695